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SR Flip-Flop Circuit

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Basic Flip-Flop Circuit:  A flipflop circuit can be constructed from two NAND gates or two NOR gates. These flip-flops are shown in Figure 4.18 and 4.19. Each flip-flop has two outputs, Q and Q' and two inputs, set and reset. This type of flip-flop is referred to as an SR flipflop or SR latch. The flipflop in Figure  has two useful states. When Q=1 and Q'=0, it is in the set state (or 1-state). When Q=0 and Q'=1, it is in the clear state (or 0-state). The outputs Q and Q' are complements of each other and are referred to as the normal and complement outputs, respectively. The binary state of the flip-flop is taken to be the value of the normal output. Logic diagram of SR Flipflop using NAND gates When a 1 is applied to both the set and reset inputs of the flip-flop in Figure , both Q and Q' outputs go to 0. This condition violates the fact that both outputs are complements of each other. In normal operation this condition must be avoided by making sure th...
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JK Flip-Flop

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A JK flipflop is a refinement of the SR flipflop, in which the indeterminate state of the SR type is defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flipflop (note that in a JK flipflop, the letter J is for set and the letter K is for clear). When logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its complement state, ie., if Q=1, it switches to Q=0 and vice versa. Logic symbol of JK Flipflop A clocked JK flip-flop is shown in Figure. Output Q is ANDed with K and CP input so that the flipflop is cleared during a clock pulse only if Q was previously 1. Similarly, output Q' is ANDed with J and CP input so that the flip-flop is set with a clock pulse only if Q' was previously 1. Note that because of the feedback connection in the JK flipflop, a CP signal which remains a 1 (while J=K=1) after the outputs have been complemented once will cause repeated and continuous transitions of the outputs. To av...
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D Flip-Flop

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The D flip-flop shown in Figure is a modification of the clocked SR flip-flop. The D input goes directly into the S input and the complement of the D input goes to the R input. The D input is sampled during the occurrence of a clock pulse. If it is 1, the flip-flop is switched to the set state (unless it was already set). If it is 0, the flip-flop switches to the clear state. Logic Symbol of D Flipflop Logic diagram of D Flipflop  Q D Q(t+1) 0 0 0 0 1 1 1 0 0 1 1 1 Transition Truth table of D Flipflop
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